Cyclic Redundant Check (CRC)

A CRC is used to verify the data transfered from CFEBs to the DAQ Mother Board, the DDU and PC.  CRC is a standard method for error check and correction in data communication.   The principle of CRC can be found in DATA COMMUNICATION reference books.

In this case, the CRC-15 is used.  The primitive function selection was based on robustness and ease of implementation in hardware.
There are 96 channels per CFEB with 8 time samples for each channel, 13 ADC bits each.  There is an ADC clock gap between each time sample.   This gap is used for CRC data insertion.  The total block data size on a CFEB for each time sample is 96 channels * 13 bits/channel = 1248 bits.  The CRC-15 primitive function is  (x**15 + x + 1).  This 15-bit CRC check word is appended to the 96 ADC words as 97th word for each time sample.  The CRC check word, with the 96 ADC data words, can be used to detect possible data transfer errors and perform limited data transfer error correction.

The CRC  hardware logic is implemented in the CFEB Multiplexer FPGA.  The CRC word is successfully readout at 150ns ADC clock period.  Lots of software simulation was carried out to test the correctness of the CRC logic, including software simulation of CRC logic, software comparison of CRC word and hardware readout result, comparison of CRC logic and full divide results.

Useful References
"Protocols & Techniques for Data Communication Networks", F. Kuo (ed.), 1981.
"The Engineer's Error Coding Handbook", A. Houghton, 1997.