CMS Endcap Muon DDU:   DMB-DDU Data Format

Proposed NEW DMB Format Version for LS1, up to 7 DCFEBs and Version ID

DMB-to-DDU Transmission   (for September 2007 CSC firmware and later)

This document describes the format structure for the Event Record arriving at the CMS Endcap Muon system Device Dependent Unit (EMU DDU).  The data originates from the Data Acquisition Motherboard (DMB) in response to a Level 1 Accept (L1A) from the trigger system.  Although the event size depends on the conditions within the cathode strip chamber (CSC), the event structure is constrained to a set of fixed format rules.  Throughout this document it is to be assumed that bits are ordered with the LSB (bit 0) on the right.

Note 1:   The current format for the 16-bit DDU input has been designed to easily interface with a 64-bit readout system through S-LINK64 (see DDU Output Format). This requires that all data sent to the DDU must have an integer multiple of 4 16-bit words for each event.   Furthermore, the highest bit of each 16-bit word from a DMB is reserved as a special flag for `DDU Code' words; since we are constrained by a 16-bit fiber-optic transmission system, only the lowest 15 bits are available for physics data.

Note 2:   The 16-bit DDU Code words are always sent in groups of 4 to make a 64-bit DDU word.  The lowest 16-bit portion of a 64-bit DDU word is the first word received by the DDU, and is designated as word "a".  The second 16-bit portion received by the DDU is word "b", the third is word "c", and the last (and highest) 16-bit part of a 64-bit DDU word is designated as word "d". The DMB-DDU word labels can be distinguished from the HEX codes in this page which use the capital letters A-F, sometimes preceded by the "0x" designator as used in C programming.

DMB-DDU Control Codes

> bit15 set HIGH indicates a special DDU Code word <
When the most significant bit of the word is high, the four most significant bits indicate the DDU Code word:
Pattern of Bits
15 14 13 12
Definition and uses for lowest 12-bits
DMB Lone Word:  L1A received, but no matching LCT on CSC, and no useful data is present.
DMB First Header Word:  Indicates that more data follows for this event.
DMB Second Header Word:  Additional DMB event information.
SCA Full :  An SCA Full condition will result in a missing time sample; the CFEB will send this word in place of data.
Status Word:  Used to pass internal board/FPGA status signals between devices.
Trigger Trailer or Header Word:  Boundary word from the TMB or ALCT for the event (generated by TMB and ALCT).
DMB Last Trailer Word:  Marks the LAST word from the DMB.
DMB First Trailer Word:  Indicates End of DMB; the NEXT word is the LAST word from the DMB.

Overview of the DMB-DDU Event Record

In an EMU DMB there are 2 types of L1A events: those that contain a local charge track segment (an "LCT") corresponding to the L1A and therefore have interesting CSC data, and those that do not have track data (the DMB "No Data" events).  This information is encoded in the first word of the DMB record as DDU Code word 9 or 8, respectively.  In the case of matching LCT.and.L1A (code word 9), additional data words follow that include the Anode LCT data, Trigger Motherboard (TMB) and Cathode LCT data, Cathode Front End Board (CFEB) data, as well as Header and Trailer words containing DDU control information.

In all cases there are time limits for DMB data arriving at the DDU: to ensure successful data handling, the first word of the DMB record must arrive at the DDU within 6.4 usec after an L1A is issued, and the last word must arrive within 236 usec after the first word arrives. Consider that the ~0.5 usec delay over the DMB-to-DDU fibers must also be taken into account.

* "if present" means that an LCTxL1A match was found on that unit

DMB-DDU Header/Trailer bit definitions (some bits get repeated for bit error mitigation)

Trigger Data Format

For a TMB or ALCT Data Word (bit15 low) Trigger Boundary (bit15 high: DDU Code 0xD)

CFEB Data Format   (for September 2007 CFEB firmware and later)

> bit15 set LOW for all data words<
For each of the 4 or 5 CFEBs on a CSC, one of three things can happen after an L1Accept:
  1. Empty:  Zero words are delivered, as this CFEB has no data (no LCT matched with the L1A).
  2. Error:  Some words are delivered, including one or more DDU Code words indicating an SCA Full or possibly a FIFO Full condition.
  3. Normal:  A series of single-time-sample data packets with 100 DMB words each (8 or 16 time samples in series form a full event).
For the 3rd case (normal data transmission), each CFEB data stream is composed of 96 SCA data words per time sample (for 12-bit digitized cathode strip data), plus 4 additional words at the end of each time sample (a CRC word, 2 status words and 1 end marker, making the word count an integer multiple of 4).  Therefore, the full word count per CFEB (CF_WC) depends on the number of time samples (N_ts) digitized:

CF_WC = {[(16 strips) * (6 layers)] + 1 CRC + 2 CFEB_INFO + 1 End_Marker} * (N_ts)

N_ts (# time samples) is set in the hardware or through slow control, typically set to 8 for LHC running (may be 16 for calibration runs), yielding CF_WC(typical)=800.

Each of the 96 SCA data words has the following format:
CFEB Data Bit Bit Definition
15 Always LOW for data words.  HIGH for DDU Code word (e.g. DMB Trailer or Error case 2 above).
14 Overlapped sample flag (normally HIGH; set LOW when two separate LCTs share a time sample).
13 Serialized CFEB-SCA controller data (trigger time and capacitor block number; see below).
12 Out of range flag from CFEB ADC.
12-bit Digitized CFEB ADC data.

The 15-bit CRC word (the 97th word in each time sample) is calculated for the set of 96 SCA data words in a time sample.  It is created using a CRC-15 algorithm (description, code, generator) with 1-bit error correct, multiple-bit error detect.  Words 98 and 99 contain CFEB Status information:

Word 99:    CFEB_L1A(6) + L1PIPE_CNT(5) + L1PIPE_WARN(1)
L1PIPE and LCTPIPE refer to CFEB-SCA Controller internal pipeline status; NF_SCA is the number of free SCA blocks (12 max).  Word 100 is the 15-bit complement of the CRC word.

CFEB Data Stream
The ordering of the words in the data stream from a single CFEB is described by the following nested loops:

do (N_ts  time samples){
do (Gray code loop over 16 CSC Strips; S=0,1,3,2,6,7,5,4,12,13,15,14,10,11,9,8){
do (loop over 6 CSC Layers; L=3,1,5,6,4,2){
SCA Data Word
CRC word
CFEB Info word 98
CFEB Info word 99
15-bit complement of the CRC word (XOR of Word 97 and 100 gives 0x7FFF)
Should an error occur, the CF_WC may deviate from this scheme (case 2 above).  Whenever that happens, a DDU Code word will be sent indicating a full condition (see below) that modifies the word count.

Serialized CFEB-SCA Controller Data
Bit 13 of each data word carries the serialized 16-bit CFEB-SCA Controller (SCAC) status word, containing trigger and SCA information.  This data word is serialized (LSB first) with one bit in each of the 16 strips read out, yielding the 16-bit word.  Due to the innermost-loop over the 6 CSC layers, each bit of a 16-bit SCAC word is actually sent 6 times in a row (once for each layer).  Since there are 16 strips read out for each time sample, the complete SCAC word can be reconstructed independently in every time sample.  The 16-bit word is defined as follows (highest-to-lowest bit):


TRIG_TIME indicates which of the eight time samples in the 400ns SCA block (lowest bit is the first sample, highest bit the eighth sample) corresponds to the arrival of the LCT; it should be a fixed phase relative to the peak of the CSC pulse.  SCA_BLK is the SCA Capacitor block used for this time sample. L1A_PHASE and LCT_PHASE show the phase of the 50ns CFEB digitization clock at the time the trigger was received (1=clock high, 0=clock low).  SCA_FULL indicates lost SCA data due to SCA full condition.  The TS_FLAG bit indicates the number of time samples to digitize per event; high=16 time samples, low=8 time samples.

SCA Full Condition

When SCA Full occurs on a CFEB, the special error word code (DDU Code 0xB) will occupy the upper 4 bits; the remaining twelve bits are described below.
 Pattern of Bits
15 14 13 12
Pattern of Bits
11 10 9
(error code)
Code Definition Lowest 9 bits [8:0]
 1011 001 CFEB: SCA Capacitors Full 0 +  4-bit Block Number + 4-bit FIFO1 word count
 1011 010 CFEB: FPGA FIFO full**  0 + 4-bit FIFO3 word count + 4-bit FIFO1 word count 
** A resynch may be required in this case.

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