CSC DAQMB Rev. 5 (Virtex2)

Data Format:  (For OSU R&D, DDU testing)

Case 1: There is CFEB data or TMB data       (for NO CFEB nor TMB data, see Case 2 below)

Header 1:  1, 0, 0, 1, Bb, Ba, B9, B8, B7, B6, B5, B4, B3, B2, B1, B0
                  B0: CFEB1 Data Available
                  B1: CFEB2 Data Available
                  B2: CFEB3 Data Available
                  B3: CFEB4 Data Available
                  B4: CFEB5 Data Available
                  B5: CFEB1 CLCT sent (Active)
                  B6: CFEB2 CLCT sent (Active)
                  B7: CFEB3 CLCT sent (Active)
                  B8: CFEB4 CLCT sent (Active)
                  B9: CFEB5 CLCT sent (Active)
                  Ba: ALCT Data Available
                  Bb: TMB Data Available 
Header 2: 1, 0, 0, 1, Bb, Ba, B9, B8, B7, B6, B5, B4, B3, B2, B1, B0
                  Bb-B0: L1ACC counter  bits[11:0]
Header 3: 1, 0, 0, 1, Bb, Ba, B9, B8, B7, B6, B5, B4, B3, B2, B1, B0
                  Bb-B0: L1ACC counter  bits[23:12]
Header 4: 1, 0, 0, 1, Bb, Ba, B9, B8, B7, B6, B5, B4, B3, B2, B1, B0
                  Bb-B0: Beam Crossing Counter  bits[11:0]
Header 5: 1, 0, 1, 0, Bb, Ba, B9, B8, B7, B6, B5, B4, B3, B2, B1, B0  (not implemented as of Nov. 15, 2002)
                  B0: CFEB1 Data Available
                  B1: CFEB2 Data Available
                  B2: CFEB3 Data Available
                  B3: CFEB4 Data Available
                  B4: CFEB5 Data Available
                  B5:  ALCT Data Available
                  B6:  TMB Data Available 
                  B7:  ALCT Data Available
                  B8:  TMB Data Available 
                  B9:  reserve (CFEB DAV-LCT mismatch)
                  Ba: ALCT Data Available
                  Bb: TMB Data Available 
Header 6: 1, 0, 1, 0, Bb, Ba, B9, B8, B7, B6, B5, B4, B3, B2, B1, B0
                  DAQMB ID.  Bb-B4: Crate ID
                                     B3-B0: Board ID
Header 7: 1, 0, 1, 0, Bb, Ba, B9, B8, B7, B6, B5, B4, B3, B2, B1, B0
                  B6-B0: Beam Crossing Counter  bits[6:0]
                  B7: CFEB1 Multi-overlap
                  B8: CFEB2 Multi-overlap
                  B9: CFEB3 Multi-overlap
                  Ba: CFEB4 Multi-overlap
                  Bb: CFEB5 Multi-overlap
Header 8: 1, 0, 1, 0, Bb, Ba, B9, B8, B7, B6, B5, B4, B3, B2, B1, B0
                  B7-B0: L1ACC counter bits[7:0]
                  Bb-B8: DMB-CFEB Sync counter bits[3:0]
TMB data, if any
          Refer to UCLA for data format
CFEB1 data, if any

   Normally, 1600 words (16 bits) in total for 16 time samples.  100 words for each time sample.  (For 8 time samples, there will be 800 words.  This is indicated in the serialized data) Bit 15 is always 0 for normal CFEB data; Bit 14 of the first 96 words in each time sample means ~OVERLAP (0 for overlap); Bit 13 of the first 96 words in each time sample is the serialized SCA capacitor and trigger information (refer to the following table). Bit [12:0] of the first 96 words are the ADC values of the 96 channels. The last four words in each time sample (word 97-100) are information words.
word # word1-6 7-12 13-18 19-24 25-30 31-36 37-42 43-48 49-54 55-60 61-66 67-72 73-78 79-84 85-90 91-96
bit 13 B0 B1 B2 B3 B4 B5 B6 B7 B8 B9 Ba Bb Bc Bd Be Bf
                   B0-B7: LCT position relative to SCA capacitors.
                   Bb-B8: SCA block number
                   Bc: L1ACC arriving time relative to 20MHz SCA clock. (1 means SCA clock high, 0 means SCA clock low)
                   Bd: LCT arriving time relative to 20MHz SCA clock
                   Be: SCA overwritten error
                   Bf: 1 for 16 time samples, 0 for 8 time samples.
          Time sample 1 data: One word (16 bits) for each channel, plus 4 information words (that is 100 words in total)
                 word 1: Layer 3, channel 0
                 word 2: Layer 1, channel 0
                 word 3: Layer 5, channel 0
                 word 4: Layer 6, channel 0
                 word 5: Layer 4, channel 0
                 word 6: Layer 2, channel 0
                 word 7-12: channel 1
                 word 13-18: channel 3
                 word 19-24: channel 2
                 word 25-30: channel 6
                 word 31-36: channel 7
                 word 37-42: channel 5
                 word 43-48: channel 4
                 word 49-54: channel 12
                 word 55-60: channel 13
                 word 61-66: channel 15
                 word 67-72: channel 14
                 word 73-78: channel 10
                 word 79-84: channel 11
                 word 85-90: channel 9
                 word 91-96: channel 8
                 word 97: CRC-15 of the previous 96 words (only the lower order 13 bits are checked)
                 word 98: 0, 1, 1, 1, Bb, Ba, B9, B8, B7, B6, B5, B4, B3, B2, B1, B0
                              B3-B0: Number of free SCA Blocks, (12 is the maximum)
                              B7-B4: LCT pipeline buffer length
                              B8: LCT pipeline buffer full
                              B9: L1ACC pipeline buffer full
                              Ba: LCT pipeline buffer empty
                              Bb: L1ACC pipeline buffer empty
                 word 99: 0, 1, 1, 1, Bb, Ba, B9, B8, B7, B6, B5, B4, B3, B2, B1, B0
                              B7-B0: L1ACC pipeline buffer length
                              B8: LCT pipeline buffer POP
                              B9: PUSH, data valid on Channel Link
                              Ba: Error, SCA overwritten
                              Bb: BUSY, system busy
                 word 100: Dummy word (7FFF)
          Time sample 2-16 data: Same data format as time sample 1 data
          In case that the SCA is full, there will be four same words '1011,001x,xxxx,xxxx' instead of 100 words for each time sample. "1011001" is a unique character for this case. Here bit 15 is set to '1', instead of '0' for normal data.
CFEB2 data, if any
       Same data format as CFEB1
CFEB3 data, if any
       Same data format as CFEB1
CFEB4 data, if any
       Same data format as CFEB1
CFEB5 data, if any
      Same data format as CFEB1
Trailer 1: 1, 1, 1, 1, Bb, Ba, B9, B8, B7, B6, B5, B4, B3, B2, B1, B0
                 Duplicate Header 1
Trailer 2: 1, 1, 1, 1, Bb, Ba, B9, B8, B7, B6, B5, B4, B3, B2, B1, B0
                  B0: CFEB1 FIFO ~Half Full (0 means more than half full, 1 means less than half full)
                  B1: CFEB2 FIFO ~Half Full (0 means more than half full, 1 means less than half full)
                  B2: CFEB3 FIFO ~Half Full (0 means more than half full, 1 means less than half full)
                  B3: CFEB4 FIFO ~Half Full (0 means more than half full, 1 means less than half full)
                  B4: CFEB5 FIFO ~Half Full (0 means more than half full, 1 means less than half full)
                  B5: Overlap FIFO ~Half Full (0 means more than half full, 1 means less than half full)
                  B6: TMB FIFO ~Half Full (0 means more than half full, 1 means less than half full)
                  B7: CFEB1 Multi-overlap
                  B8: CFEB2 Multi-overlap
                  B9: CFEB3 Multi-overlap
                  Ba: CFEB4 Multi-overlap
                  Bb: CFEB5 Multi-overlap
Trailer 3: 1, 1, 1, 1, Bb, Ba, B9, B8, B7, B6, B5, B4, B3, B2, B1, B0
                 B3-B0: Beam Crossing counter bits[3:0]
                 Bb-B4: L1ACC pipeline length in DAQMB Controller FPGA
Trailer 4: 1, 1, 1, 1, Bb, Ba, B9, B8, B7, B6, B5, B4, B3, B2, B1, B0
                 Duplicate Header 6, DAQMB ID
Trailer 5: 1, 1, 1, 0, Bb, Ba, B9, B8, B7, B6, B5, B4, B3, B2, B1, B0
                 B0: CFEB1 FIFO ~Empty (0 means empty, 1 means not empty)
                 B1: CFEB2 FIFO ~Empty (0 means empty, 1 means not empty)
                 B2: CFEB3 FIFO ~Empty (0 means empty, 1 means not empty)
                 B3: CFEB4 FIFO ~Empty (0 means empty, 1 means not empty)
                 B4: CFEB5 FIFO ~Empty (0 means empty, 1 means not empty)
                 B5: TMB FIFO ~Empty (0 means empty, 1 means not empty)
                 B6: CFEB1 FIFO ~Full (0 means full, 1 means not full)
                 B7: CFEB2 FIFO ~Full (0 means full, 1 means not full)
                 B8: CFEB3 FIFO ~Full (0 means full, 1 means not full)
                 B9: CFEB4 FIFO ~Full (0 means full, 1 means not full)
                 Ba: CFEB5 FIFO ~Full (0 means full, 1 means not full)
                 Bb: TMB FIFO ~Full (0 means full, 1 means not full)
Trailer 6: 1, 1, 1, 0, Bb, Ba, B9, B8, B7, B6, B5, B4, B3, B2, B1, B0
                 B0: There is no CFEB1 data when data readout
                 B1: There is no CFEB2 data when data readout
                 B2: There is no CFEB3 data when data readout
                 B3: There is no CFEB4 data when data readout
                 B4: There is no CFEB5 data when data readout
                 B5: There is no TMB data when data readout (start and/or end timeout)
                 B6: There is no end of CFEB1 data when data readout
                 B7: There is no end of CFEB2 data when data readout
                 B8: There is no end of CFEB3 data when data readout
                 B9: There is no end of CFEB4 data when data readout
                 Ba: There is no end of CFEB5 data when data readout
                 Bb: There is no ALCT data when data readout (start and/or end timeout)
Trailer 7: 1, 1, 1, 0, Bb, Ba, B9, B8, B7, B6, B5, B4, B3, B2, B1, B0
                 Duplicate Trailer 6
Trailer 8: 1, 1, 1, 0, Bb, Ba, B9, B8, B7, B6, B5, B4, B3, B2, B1, B0
                 Duplicate Trailer 6 (also same as trailer 7)

Case 2: There is no CFEB data, nor TMB data:

Header 1: 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0
Header 2: 1, 0, 0, 0, Bb, Ba, B9, B8, B7, B6, B5, B4, B3, B2, B1, B0
                  Bb-B0: L1ACC counter bits[11:0]
Header 3: 1, 0, 0, 0, Bb, Ba, B9, B8, B7, B6, B5, B4, B3, B2, B1, B0
                  Bb-B0: L1ACC counter bits[23:12]
Header 4: 1, 0, 0, 0, Bb, Ba, B9, B8, B7, B6, B5, B4, B3, B2, B1, B0
                  Bb-B0: Beam Crossing Counter bits[11:0]

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