Xilinx Virtex DLL and Data Delay Device 3D7408 test results

Test setup: Chips used: Xilinx xcv50-4-pq240 and Data Dealy Device 3D7408-0.25-SOIC
Here is the block diagram of the test setup and this is the FPGA design.  The Delay chip is set to Transparent Parallel Mode, and controled by the registers inside the FPGA.
DLL test Results:

Delay chip (3D7408) test results:

Preliminary version finished:  Feb. 25, 2002.

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