Fake Backplane (FBP) for DAQMB

The FBP simulate the CCB and TMB signals and plug in DAQMB directly.  Here is the Schematic design of the FBP, and here is the schematic design of the FPGA on the FBP.  The MCS file to download the PROM for the current version of FPGA design is here.

Operation of the FBP.
The FBP supplys 40MHz clock, which is the main control clock for DAQMB and configuration clock for the FPGAs.  By toggling SW7 and 8, the DAQMB FPGAs are reprogrammed.  By pushing the RST momentary switch, the DAQMB gets a RESET.  (For SW7, SW8, RST, look on the PCB board for labeling).
Power requirement:  The FBP requires +5V and +3.3 V through an 8-pin power connector.  The 2.5V for Virtex FPGA and 1.5V for GTLP termination are generated on board through regulators.
Verifying the FBP status. The power LEDs (+5V, +3.3V, located nears the FUSEs) should be ON.  The Program LED (located near the XC1701L PROM) should blink when powerup.

External Trigger using FBP (Specially useful for JINR for ME1/1).
The BNC connectors on the FBP can be used for external trigger.  There is a 50Ohm termination resistor on the FBP LCT input (LVTTL expected).
Switch setting:  On DAQMB: set SW1, SW2, SW4 switches near the controller FPGA, XCV200E to 'OFF' (or 'OPEN' for some switch labeling) position, so they are logic HIGH.  On FBP, set SW1, SW2, SW3, SW4, SW5 and SW6 to 'ON' (or 'CLOSE' for some switch labeling) position, so they are logic HIGH; set SWA1 to ON, SWA2 to OFF, SWA3 to OFF and SWA4 to ON position, so that the L1ACC delay relative to LCT seen on CFEB will be 2900ns.  Connect the external trigger source (TTL, 50Ohm terminated on the FBP) to the BNC connector labeled 'LCT'.  The FBP will sync the input and send to DAQMB/CFEB as LCT, and FBP will also generate L1ACC after a delay.

Last modified: June 17,  2002.

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