This page contains the schematic pages for the Linker Tester card.  The files are postscript documents: 

• Block Diagram
• The Channel Link Drivers:
• Connectors and Channel Links 0, 1
• Channel Links 2, 3, 4, 5
• Channel Links 6, 7, 8, 9
• Channel Link 10
• The Channel Link Fifos
• Fifos 0, 1 and Debug headers J902, J903, J904, J905
• Fifos 2, 3, 4
• Fifos 5, 6, 7
• Fifos 8, 9, 10
• Fifos 11, 12, 13
• Fifos 14, 15
• The XTRP Receiver Fifos
• Receiver Fifos 0, 1, Debug Headers J4, J906
• Receiver Fifos 2, 3
• LVDS Receivers from Linker, J3 Connector
• The VME/Control Chip, Debug Header J901
• JTAG, Clock Section
• VME Buffers page 1
• VME Buffers page 2
• J1 Connector
• J2 Connector
• Discharge Strips, Stiffener, Fuses

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