Gigabit Ethernet VME Crate Controller (VCC)

 

  • Hardware:

o    Schematics (pdf):   http://www.physics.ohio-state.edu/~cms/GbE_Ctrl/sch_icon.png

    • Photos of prototype:   http://www.physics.ohio-state.edu/~cms/GbE_Ctrl/VME_ctrl_2_icon.gif   http://www.physics.ohio-state.edu/~cms/GbE_Ctrl/VME_ctrl_1_icon.gif

 

 

Firmware Revision Table

(Step by step instructions for loading firmware using Xilinx Parallel Cable IV and iMPACT)

This table is now in reverse time order (most recent files at the top).

Revision

Date

Schematic

Verilog Source Code1

PROM Files2,3

Comments

*4.9A

8/26/15

mcs, zip

Modified startup/shutdown procedures (releases VME bus immediately on shutdown).(Current Default Version)

4.7C

8/12/13

mcs, zip

Same as version 4.74 but compiled specifically for pre-production VCCs.

4.74

6/11/09

 

 

 mcs, zip

Auto Negotiate added for link initialization with switch.  7 version with different place & route.

4.73-4.7B

6/11/09

 

 

 zip

Auto Negotiate added for link initialization with switch.  7 version with different place & route.

4.4C

11/15/08

 

 

mcs, zip

Reroute 

4.4B

11/15/08

 

 

mcs, zip

Reroute

4.4A

11/3/08

 

 

mcs, zip

 

4.38

07/2/2008

 

 

mcs, zip

Fixed a bug that causes unexpected "null" error packets.

4.31

02/18/2008

 

 

mcs, zip

Fixed packet "type" bug that affected external FIFO testing.

4.30

02/13/2008

pdf

zip, tgz

zip

Fixes for issues found with first version 4 release.  1) FPGA reloads work reliably.  2) Protection for MAC address mix-up on FIFO overflows.  3) Data packet returned on BERR even with errors disabled.

4.29

01/21/2008

pdf

zip, tgz

zip

Version 4 release.  Updated firmware defaults for config. registers.

4.28

01/09/2008

 

 

zip

Version 4 release.  JTAG interface to PROM allows programming via ethernet.

4.08

09/20/2007

 

 

zip

First beta release of version 4.  Features: packet acknowledgements, command completion status, universal error codes, MAC source tracking with command progress (improves return packet destination accuracy), optional BERR masking, and more.  Not yet implemented: JTAG interface to PROM to allow programming via ethernet.

3.71

04/04/2007

 

 

zip

Same as above but recompiled with no register duplication.

3.70

04/03/2007

 

 

zip

Minor changes in VME master to test problem with TMB to MPC test program. ("Last_Cycle" extended to "Xfer_Done" state, Sync registers in IOB's)

3.6F

10/27/2006

pdf

zip, tgz

zip

Fixes a bug found in writing destination MAC addresses in return packets. 

3.6A

10/13/2006

 

 

zip

Implementation of VME rules adjusted to for 8ns system clock (used to be based on a 4ns clock).

3.69

10/04/2006

 

 

zip

Same as 3.68 but DCM monitoring and startup sequence has been made more robust. So far this seems to be good compile.

3.68

10/03/2006

 

 

zip

Doubled system clock period from 4ns to 8ns. This affects VME timing and has not been thoroughly tested.

3.67

10/02/2006

 

 

zip

Reconfigured clock managament, and startup proceedures.

3.60

9/11/2006

 

 

zip

No logic changes, simply recompiled with ISE 8.202i

3.59

4/5/2006

pdf

zip, tgz

zip

Fixed several bugs.  An internal timing problem caused bus request during wrong states.  This compiled version has good timing.  Implemented a Bus Grant time-out error.  Fixed some default MAC issues noted by Jinghua.  Implemented 'Force_Reload' (still F9) command upstream of buffering and command processing.  This "high priority" reload command should work even when other command processing is "hung".  This only requires an established fiber link, a stable clock, and DLL lock.

3.55

3/8/2006

pdf

zip, tgz

zip

Added error handling in VME control and in VME master for bus errors (BERR); Packet type codes for INFO/WARN/ERR and INTR has changed; defined a format for identifying INFO/WARN/ERR sources; Redefined INFO/WARN/ERR message formats; Added interrupt handler module; Changed VME_config register definitions and defaults.  Added functions for writing and reading serial numbers to/from FLASH;    Extensively tested and tweaked VME interface to make it less sensitive to backplane noise and glitches; Added Wrt_CR_ID (write Cnfg reg. based on ID) function; Redefined front panel switch 2; Added BOD (Beginning Of Data) marking in external FIFO to separate packets of VME data to facilitate error recovery; Changed slow clock generation method to utilize SRLs (area efficient); Optimized some areas of VME interface to improve timing issues.

pre-prod zip

3.06

8/31/2005

pdf

zip, tgz

zip

Return data header format change (now 4 header words)! Flash memory functions implemented (MAC addresses and Config. Reg.'s). Separate path for spontaneous packets (Errors, Warnings, Information, and Interrupts).

2.22

8/11/2005

 

 

zip

Corrected timing issues, auto slot 1 id, fixed bus arbitration/request issues.

2.19

7/21/2005

 

 

mcs

Slight adjustment to trailing edge of the Data Strobes (DS0, DS1)

2.18

7/8/2005

 

 

mcs, svf

Startup packet disabled; Info and warning types added;

2.17

7/5/2005

 

 

mcs

Sends a packet on startup; (Radiation test version)

 

 

 

 

 

 

1The Verilog source files are either zipped with WINzip on a Windows system or tar'd and gzipped on a Linux system.

2Zipped versions contain supplemental files necessary for proper revisioning setup in XCFP08 PROM when programming with IMPACT.

3SVF versions are for use when programming via Ethernet using the provided custom software utility (not yet available).

 

 

Software: